  
module top( 
  input clk_50M,
  input reset,
  output [4:0] led,
  
  output D26,//uart out
//  5V
//GND
output C26,
output F24,
input  F27,
input  H21,
input  E26,
input  J24,
input  K27,
input  K22,

  input USB3_UART_IN,

output GPIO0,
output GPIO1,
output GPIO2,
output GPIO3,
output GPIO4,
output GPIO5,
output GPIO6,
output GPIO7,
output GPIO8,
output GPIO9,
output GPIO10,
output GPIO11,
output GPIO12,
output GPIO13,
output GPIO14,
output GPIO15,
output GPIO16,
output GPIO17,
output GPIO18,
output GPIO19,
output GPIO20,
output GPIO21,
output GPIO22,
output GPIO23,
output GPIO24,
output GPIO25,
output GPIO26,
output GPIO27,
output GPIO28,
output GPIO29,
output GPIO33,
output GPIO34,
output GPIO35,
output GPIO36,
output GPIO37,
output GPIO38,
output GPIO39,
output GPIO40,
output GPIO41,
output GPIO42,
output GPIO43,
output GPIO44,
output GPIO45,
output GPIO46,
output GPIO47,
output GPIO48,
output GPIO49,
//output GPIO50,
output GPIO51,
output GPIO52,
output GPIO53,
output GPIO54,
output GPIO56,
output GPIO57,


  input dummy
);

wire sys_rst_n;
assign sys_rst_n = reset;// && locked_sdram && locked_cpu && locked_vga;

//assign debug = flg;
assign D26 = USB3_UART_IN;


assign led[0] = ~C26;
assign led[1] = ~F24;
assign led[2] = H21;
assign led[3] = ~E26;
assign led[4] = J24;

reg [31:0] cnt;
reg flg;
always @(posedge clk_50M or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    cnt <= 0;
    flg <= 1;
  end else begin
    cnt <= cnt+1'b1;
	 if(cnt==32'd50000000)begin
		cnt <= 0;
		flg <= ~flg;
	 end
  end
end
assign indata = 0;

wire [31:0] debug_address_out;

assign GPIO0 = debug_address_out == 0  ? flg : 1'bz;
assign GPIO1 = debug_address_out == 1  ? flg : 1'bz;
assign GPIO2 = debug_address_out == 2  ? flg : 1'bz;
assign GPIO3 = debug_address_out == 3  ? flg : 1'bz;
assign GPIO4 = debug_address_out == 4  ? flg : 1'bz;
assign GPIO5 = debug_address_out == 5  ? flg : 1'bz;
assign GPIO6 = debug_address_out == 6  ? flg : 1'bz;
assign GPIO7 = debug_address_out == 7  ? flg : 1'bz;
assign GPIO8 = debug_address_out == 8  ? flg : 1'bz;
assign GPIO9 = debug_address_out == 9  ? flg : 1'bz;
assign GPIO10= debug_address_out == 10 ? flg : 1'bz;
assign GPIO11= debug_address_out == 11 ? flg : 1'bz;
assign GPIO12= debug_address_out == 12 ? flg : 1'bz;
assign GPIO13= debug_address_out == 13 ? flg : 1'bz;
assign GPIO14= debug_address_out == 14 ? flg : 1'bz;
assign GPIO15= debug_address_out == 15 ? flg : 1'bz;
assign GPIO16= debug_address_out == 16 ? flg : 1'bz;
assign GPIO17= debug_address_out == 17 ? flg : 1'bz;
assign GPIO18= debug_address_out == 18 ? flg : 1'bz;
assign GPIO19= debug_address_out == 19 ? flg : 1'bz;
assign GPIO20= debug_address_out == 20 ? flg : 1'bz;
assign GPIO21= debug_address_out == 21 ? flg : 1'bz;
assign GPIO22= debug_address_out == 22 ? flg : 1'bz;
assign GPIO23= debug_address_out == 23 ? flg : 1'bz;
assign GPIO24= debug_address_out == 24 ? flg : 1'bz;
assign GPIO25= debug_address_out == 25 ? flg : 1'bz;
assign GPIO26= debug_address_out == 26 ? flg : 1'bz;
assign GPIO27= debug_address_out == 27 ? flg : 1'bz;
assign GPIO28= debug_address_out == 28 ? flg : 1'bz;
assign GPIO29= debug_address_out == 29 ? flg : 1'bz;
assign GPIO33= debug_address_out == 33 ? flg : 1'bz;
assign GPIO34= debug_address_out == 34 ? flg : 1'bz;
assign GPIO35= debug_address_out == 35 ? flg : 1'bz;
assign GPIO36= debug_address_out == 36 ? flg : 1'bz;
assign GPIO37= debug_address_out == 37 ? flg : 1'bz;
assign GPIO38= debug_address_out == 38 ? flg : 1'bz;
assign GPIO39= debug_address_out == 39 ? flg : 1'bz;
assign GPIO40= debug_address_out == 40 ? flg : 1'bz;
assign GPIO41= debug_address_out == 41 ? flg : 1'bz;
assign GPIO42= debug_address_out == 42 ? flg : 1'bz;
assign GPIO43= debug_address_out == 43 ? flg : 1'bz;
assign GPIO44= debug_address_out == 44 ? flg : 1'bz;
assign GPIO45= debug_address_out == 45 ? flg : 1'bz;
assign GPIO46= debug_address_out == 46 ? flg : 1'bz;
assign GPIO46= debug_address_out == 46 ? flg : 1'bz;
assign GPIO47= debug_address_out == 47 ? flg : 1'bz;
assign GPIO48= debug_address_out == 48 ? flg : 1'bz;
assign GPIO49= debug_address_out == 49 ? flg : 1'bz;
//assign GPIO50= debug_address_out == 50 ? flg : 1'bz;
assign GPIO51= debug_address_out == 51 ? flg : 1'bz;
assign GPIO52= debug_address_out == 52 ? flg : 1'bz;
assign GPIO53= debug_address_out == 53 ? flg : 1'bz;
assign GPIO54= debug_address_out == 54 ? flg : 1'bz;
assign GPIO56= debug_address_out == 56 ? flg : 1'bz;
assign GPIO57= debug_address_out == 57 ? flg : 1'bz;



debugger_ch341a_ft232h debugger_ch341a_ft232h_inst (
    .clk(clk_50M),
    .clk_50M(clk_50M),
    .reset_n(sys_rst_n),

    .ch341a_miso(C26),//d7 data out
    .ch341a_ack (F24), //d6 debug
    .ch341a_mosi(F27),//d5
	//            H21  //d4
    .ch341a_sck (E26), //d3
    .ch341a_cs2 (J24), //d2 data out
    .ch341a_cs1 (K27), //d1 data in
    .ch341a_cs0 (K22), //d0 cmd in /data out

	 .debug_address_out(debug_address_out),

    .dummy(dummy)
);


/*

NET "ch341a_miso"   		LOC = K5  	| IOSTANDARD = LVTTL;
NET "ch341a_ack"    		LOC = L4  	| IOSTANDARD = LVTTL;
#
NET "ch341a_mosi"  		LOC = D9 	| IOSTANDARD = LVTTL;
NET "ch341a_sck"  		LOC = E11 	| IOSTANDARD = LVTTL;
NET "ch341a_cs2"  		LOC = E13 	| IOSTANDARD = LVTTL;
NET "ch341a_cs1"  		LOC = K12 	| IOSTANDARD = LVTTL;
NET "ch341a_cs0"  		LOC = N4 	| IOSTANDARD = LVTTL;
NET "ch341a_sck" CLOCK_DEDICATED_ROUTE = FALSE;

NET "ch341a_sck" TNM_NET = ch341a_sck;
TIMESPEC TS_ch341a_sck = PERIOD "ch341a_sck" 5 MHz HIGH 50%;
NET "ch341a_mosi" OFFSET = IN 500 ns VALID 500 ns BEFORE "ch341a_sck" RISING;
NET "ch341a_miso" OFFSET = OUT 500 ns AFTER "ch341a_sck";


	Gnd	Vcc	
L	K5 ,	K6 ,	R
1	L4 ,	L5 ,	1
2	M1 ,	E8 ,	2
3	D9 ,	F10,	3
4	E11,	E12,	4
5	E13,	F12,	5
6	K12,	M5 ,	6
7	N4 ,	M4 ,	7
	x	x	






*/
endmodule
